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» Robustness of Sequential Circuits
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ASPDAC
2004
ACM
145views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Hierarchical random-walk algorithms for power grid analysis
Abstract— This paper presents a power grid analyzer that combines a divide-and-conquer strategy with a random-walk engine. A single-level hierarchical method is first described ...
Haifeng Qian, Sachin S. Sapatnekar
ASPDAC
2008
ACM
129views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Clock tree synthesis with data-path sensitivity matching
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
CICC
2011
106views more  CICC 2011»
12 years 8 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
ICCAD
2008
IEEE
116views Hardware» more  ICCAD 2008»
14 years 5 months ago
Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example
—Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-sp...
Ranko Sredojevic, Vladimir Stojanovic
ISCAS
2008
IEEE
129views Hardware» more  ISCAS 2008»
14 years 3 months ago
Physical unclonable function with tristate buffers
— The lack of robust tamper-proofing techniques in security applications has provided attackers the ability to virtually circumvent mathematically strong cryptographic primitive...
Erdinç Öztürk, Ghaith Hammouri, B...