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» Robustness of Sequential Circuits
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VLSID
1997
IEEE
135views VLSI» more  VLSID 1997»
14 years 1 months ago
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxen...
DAC
1995
ACM
14 years 15 days ago
The Validity of Retiming Sequential Circuits
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
Vigyan Singhal, Carl Pixley, Richard L. Rudell, Ro...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 2 months ago
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, S...
TCAD
1998
110views more  TCAD 1998»
13 years 8 months ago
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG
—New methods for fault-effect propagation and state justification that use finite-state-machine sequences are proposed for sequential circuit test generation. Distinguishing se...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
VLSID
2005
IEEE
255views VLSI» more  VLSID 2005»
14 years 9 months ago
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher ord...
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. ...