768 search results - page 31 / 154 » Robustness of Sequential Circuits |
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
Iterative retiming and resynthesis is a powerful way to optimize sequential circuits but its massive adoption has been hampered by the hardness of verification. This paper tackle...
DFT
2006
IEEE
14 years 17 days ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
EH
2003
IEEE
14 years 2 months ago
2003
IEEE
The evolution of circuits with on-line built-in self-test is attempted in simulation for a full adder, a two bit multiplier and an edge triggered D-Latch. Results show that evolve...
IH
2004
Springer
14 years 2 months ago
2004
Springer
In this paper, we consider how to hide information into finite state machine (FSM), one of the popular computation models. The key advantage of hiding information in FSM is that t...