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AHS
2006
IEEE
113views Hardware» more  AHS 2006»
14 years 16 days ago
A Honeycomb Development Architecture for Robust Fault-Tolerant Design
A new hardware developmental model that shows strong robust transient fault-tolerant abilities and is motivated by embryonic development and a honeycomb structure is presented. Ca...
Andy M. Tyrrell, Hong Sun
ETS
2009
IEEE
98views Hardware» more  ETS 2009»
13 years 6 months ago
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
Stephan Eggersglüß, Rolf Drechsler
GW
2005
Springer
120views Biometrics» more  GW 2005»
14 years 2 months ago
Recognition of Deictic Gestures for Wearable Computing
In modern society there is an increasing demand to access, record and manipulate large amounts of information. This has inspired a new approach to thinking about and designing pers...
Thomas B. Moeslund, Lau Nørgaard
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Process variation robust clock tree routing
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
Wai-Ching Douglas Lam, Cheng-Kok Koh
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 3 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy