A new hardware developmental model that shows strong robust transient fault-tolerant abilities and is motivated by embryonic development and a honeycomb structure is presented. Ca...
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
In modern society there is an increasing demand to access, record and manipulate large amounts of information. This has inspired a new approach to thinking about and designing pers...
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...