116 search results - page 19 / 24 » Route Packets, Not Wires: On-Chip Interconnection Networks |
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
Minimizing latency and maximizing throughput are important goals in the design of routing algorithms for interconnection networks. Ideally, we would like a routing algorithm to (a...
JCM
2006
13 years 8 months ago
2006
In this paper, we propose and analyze a multicast application called SOMA (SynchrOnous Multicast Application) which offers multicast file transfer service in an asymmetric intra-ca...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
NPC
2004
Springer
14 years 1 months ago
2004
Springer
Massively parallel computing systems are being built with thousands of nodes. Because of the high number of components, it is critical to keep these systems running even in the pre...
PRDC
2005
IEEE
14 years 2 months ago
2005
IEEE
An important issue in modern cache designs is bridging the gap between wire and device delays. This warrants the use of more regular and modular structures to mask wire latencies....