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» Route Packets, Not Wires: On-Chip Interconnection Networks
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HPCA
2008
IEEE
14 years 9 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
14 years 1 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
ISCAPDCS
2004
13 years 10 months ago
The Fat-Stack and Universal Routing in Interconnection Networks
This paper shows that a novel network called the fat-stack is universally efficient when adequate capacity distribution is provided and is suitable for use as an interconnection n...
Kevin F. Chen, Edwin Hsing-Mean Sha
ASPLOS
2010
ACM
13 years 12 months ago
A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing
We present an all-optical approach to constructing data networks on chip that combines the following key features: (1) Wavelengthbased routing, where the route followed by a packe...
Nevin Kirman, José F. Martínez
HSNMC
2003
Springer
106views Multimedia» more  HSNMC 2003»
14 years 1 months ago
RD-TCP: Reorder Detecting TCP
Abstract. Numerous studies have shown that packet reordering is common, especially in high speed networks where there is high degree of parallelism and different link speeds. Reor...
Arjuna Sathiaseelan, Tomasz Radzik