830 search results - page 81 / 166 » Route kernels for trees |
135
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DAC
2008
ACM
16 years 5 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
176
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CN
2004
15 years 4 months ago
2004
In this paper, we introduce a new IP lookup scheme with worst-case search and update time of O(log n), where n is the number of prefixes in the forwarding table. Our scheme is base...
111
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NOCS
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network [6]. Unlike previous clustered mesh a...
112
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GECCO
2005
Springer
15 years 9 months ago
2005
Springer
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...
129
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ICCAD
1994
IEEE
15 years 8 months ago
1994
IEEE
We give the rst single-layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear-Planar-DME method 11 guarantees a planar solutio...