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» Routers with Very Small Buffers
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ISPASS
2009
IEEE
14 years 4 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
MICRO
2002
IEEE
156views Hardware» more  MICRO 2002»
13 years 9 months ago
TCP Switching: Exposing Circuits to IP
There has been much discussion about the best way to combine the benefits of new optical circuit switching technology with the established packet switched Internet. In this paper,...
Pablo Molinero-Fernández, Nick McKeown
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
14 years 3 months ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...
NCA
2003
IEEE
14 years 3 months ago
Scalable Protocol for Content-Based Routing in Overlay Networks
In content networks, messages are routed on the basis of their content and the interests (subscriptions) of the message consumers. This form of routing offers an interesting alte...
Raphaël Chand, Pascal Felber
FPL
2006
Springer
96views Hardware» more  FPL 2006»
14 years 1 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling