179 search results - page 7 / 36 » Routing for Energy Minimization in the Speed Scaling Model |
SAC
2010
ACM
13 years 7 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
We present an optimal and scalable permutation routing algorithm for three reconfigurable models based on linear arrays that allow pipelining of information through an optical bus...
CSE
2009
IEEE
13 years 10 months ago
2009
IEEE
— Low energy consumption is a critical issue in embedded systems design. As the technology feature sizes of SoC (Systems on Chip) become smaller and smaller, the percentage of le...
TVLSI
2010
13 years 2 months ago
2010
With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fail...
MICROMACHINES
2011
13 years 2 months ago
2011
: A wealth of current research in microengineering aims at fabricating devices of increasing complexity, notably by (self-)assembling elementary components into heterogeneous funct...