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» Routing in a cyclic mobispace
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ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 11 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
HPCC
2007
Springer
14 years 4 months ago
Systolic Routing in an Optical Ring with Logarithmic Shortcuts
Abstract. We present an all-optical ring network architecture with logarithmic shortcuts and a systolic routing protocol for it. An r-dimensional optical ring network with logarith...
Risto Honkanen, Juha-Pekka Liimatainen
SIROCCO
2001
13 years 11 months ago
Characterization of Networks Supporting Multi-dimensional Linear Interval Routing Schemes
An Interval Routing Scheme (IRS) is a well-known, space efficient routing strategy for routing messages in a distributed network. In this scheme, each node of the network is assig...
Yashar Ganjali
GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
13 years 11 months ago
Resource-constrained timing-driven link insertion for critical delay reduction
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
Jin-Tai Yan, Zhi-Wei Chen
CSREAESA
2010
13 years 7 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton