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» Routing in the frequency domain
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DAC
2004
ACM
14 years 8 months ago
Profile-guided microarchitectural floorplanning for deep submicron processor design
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watew...
DAC
2006
ACM
14 years 8 months ago
An adaptive FPGA architecture with process variation compensation and reduced leakage
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
Georges Nabaa, Navid Azizi, Farid N. Najm
HPCA
2009
IEEE
14 years 8 months ago
Elastic-buffer flow control for on-chip networks
This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel b...
George Michelogiannakis, James D. Balfour, William...
SC
2009
ACM
14 years 2 months ago
Router designs for elastic buffer on-chip networks
This paper explores the design space of elastic buffer (EB) routers by evaluating three representative designs. We propose an enhanced two-stage EB router which maximizes through...
George Michelogiannakis, William J. Dally
ICASSP
2008
IEEE
14 years 2 months ago
Optimal FDMA over wireless fading mobile ad-hoc networks
We formulate a frequency-division multiple access (FDMA) networking problem for wireless mobile ad-hoc networks (MANETS) to jointly optimize end-to-end user rates, routes, link ca...
Alejandro Ribeiro, Georgios B. Giannakis