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DAC
2006
ACM
14 years 10 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
FPL
2000
Springer
128views Hardware» more  FPL 2000»
14 years 1 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght
BCS
2008
13 years 11 months ago
Tools for Traceable Security Verification
Dependable systems evolution has been identified by the UK Computing Research Committee (UKCRC) as one of the current grand challenges for computer science. We present work toward...
Jan Jürjens, Yijun Yu, Andreas Bauer 0002
DAC
2010
ACM
13 years 11 months ago
An efficient dual algorithm for vectorless power grid verification under linear current constraints
Vectorless power grid verification makes it possible to evaluate worst-case voltage drops without enumerating possible current waveforms. Under linear current constraints, the vec...
Xuanxing Xiong, Jia Wang
CADE
2008
Springer
14 years 10 months ago
Precise Dynamic Verification of Confidentiality
Confidentiality is maybe the most popular security property to be formally or informally verified. Noninterference is a baseline security policy to formalize confidentiality of sec...
Gurvan Le Guernic