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DAC
2004
ACM
14 years 12 months ago
Abstraction refinement by controllability and cooperativeness analysis
ion Refinement by Controllability and Cooperativeness Analysis Freddy Y.C. Mang and Pei-Hsin Ho Advanced Technology Group, Synopsys, Inc. {fmang, pho}@synopsys.com nt a new abstrac...
Freddy Y. C. Mang, Pei-Hsin Ho
DAC
2005
ACM
14 years 12 months ago
Simulation based deadlock analysis for system level designs
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. S...
PADL
2009
Springer
14 years 11 months ago
Operational Semantics for Declarative Networking
Declarative Networking has been recently promoted as a high-level programming paradigm to more conveniently describe and implement systems that run in a distributed fashion over a ...
Juan A. Navarro, Andrey Rybalchenko
ASPDAC
2006
ACM
137views Hardware» more  ASPDAC 2006»
14 years 5 months ago
Parameterized block-based non-gaussian statistical gate timing analysis
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
14 years 3 months ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...