252 search results - page 12 / 51 » Runtime Verification Using a Temporal Description Logic |
TCS
2008
13 years 7 months ago
2008
Starting from the logical description of gene regulatory networks developed by R. Thomas, we introduce an enhanced modelling approach based on timed automata. We obtain a refined ...
ICFEM
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. Due to new emerging areas in the communication field there is a constant need for the design of novel communication protocols. This demands techniques for a rapid and eff...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DAGSTUHL
2006
13 years 9 months ago
2006
We examine the possible use of Description Logics as a knowledge representation and reasoning system for high-level scene interpretation. It is shown that aggregates composed of m...
CADE
2002
Springer
14 years 8 months ago
2002
Springer
Abstract. We investigate the combination of propositional SAT checkers with domain-specific theorem provers as a foundation for bounded model checking over infinite domains. Given ...