Sciweavers

11 search results - page 2 / 3
» Runtime identification of microprocessor energy saving oppor...
Sort
View
SC
2005
ACM
14 years 1 months ago
A Power-Aware Run-Time System for High-Performance Computing
For decades, the high-performance computing (HPC) community has focused on performance, where performance is defined as speed. To achieve better performance per compute node, mic...
Chung-Hsing Hsu, Wu-chun Feng
DAC
2007
ACM
14 years 8 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
DATE
2005
IEEE
129views Hardware» more  DATE 2005»
14 years 1 months ago
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling
A novel energy reduction strategy to maximally exploit the dynamic workload variation is proposed for the offline voltage scheduling of preemptive systems. The idea is to construc...
Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu
HPCA
2008
IEEE
14 years 7 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
CF
2005
ACM
13 years 9 months ago
A case for a working-set-based memory hierarchy
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...
Steve Carr, Soner Önder