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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 4 months ago
Performance Efficiency of Context-Flow System-on-Chip Platform
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective program...
Rami Beidas, Jianwen Zhu
DAC
2007
ACM
14 years 9 months ago
A New Twisted Differential Line Structure in Global Bus Design
Twisted differential line structure can effectively reduce crosstalk noise on global bus, which foresees a wide applicability. However, measured performance based on fabricated ci...
Zhanyuan Jiang, Shiyan Hu, Weiping Shi
JCP
2008
118views more  JCP 2008»
13 years 8 months ago
Power-efficient Instruction Encoding Optimization for Various Architecture Classes
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
Diandian Zhang, Anupam Chattopadhyay, David Kammle...
NOCS
2009
IEEE
14 years 2 months ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 8 months ago
A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan