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PPL
2008
185views more  PPL 2008»
13 years 7 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
GLOBECOM
2006
IEEE
14 years 2 months ago
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
Andrea Bianco, Jorge M. Finochietto, Giulio Galant...
FPL
2008
Springer
153views Hardware» more  FPL 2008»
13 years 9 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 4 months ago
Fast and accurate transaction level models using result oriented modeling
Efficient communication modeling is a critical task in SoC design and exploration. In particular, fast and accurate communication is needed to predict the performance of a system....
Gunar Schirner, Rainer Dömer
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
14 years 1 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...