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» SAT-Based Algorithms for Logic Minimization
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DAC
2003
ACM
14 years 8 months ago
On-chip logic minimization
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
Roman L. Lysecky, Frank Vahid
WEA
2010
Springer
397views Algorithms» more  WEA 2010»
14 years 1 months ago
A New Combinational Logic Minimization Technique with Applications to Cryptology
Abstract. A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the nonlinearity of a circuit – as measured ...
Joan Boyar, René Peralta
CODES
2003
IEEE
14 years 9 days ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
STOC
2006
ACM
170views Algorithms» more  STOC 2006»
14 years 7 months ago
Hardness of approximate two-level logic minimization and PAC learning with membership queries
Producing a small DNF expression consistent with given data is a classical problem in computer science that occurs in a number of forms and has numerous applications. We consider ...
Vitaly Feldman
TMC
2012
11 years 9 months ago
E-MiLi: Energy-Minimizing Idle Listening in Wireless Networks
WiFi interface is known to be a primary energy consumer in mobile devices, and idle listening (IL) is the dominant source of energy consumption in WiFi. Most existing protocols, s...
Xinyu Zhang, Kang G. Shin