149 search results - page 26 / 30 » SAT-based Unbounded Model Checking of Timed Automata |
DBPL
2007
Springer
14 years 1 months ago
2007
Springer
Macro tree transducers (mtt) are an important model that both covers many useful XML transformations and allows decidable exact typechecking. This paper reports our first step tow...
VMCAI
2010
Springer
14 years 2 months ago
2010
Springer
This paper upgrades Regular Linear Temporal Logic (RLTL) with past operators and complementation. RLTL is a temporal logic that extends the expressive power of linear temporal logi...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
Abstract. We propose an approach to scenario-based analysis and synthesis of real-time embedded systems. The inter-process behaviors of a system are modeled as a set of driving uni...
CHARME
2003
Springer
13 years 11 months ago
2003
Springer
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...
ASE
2002
13 years 7 months ago
2002
This paper describes a specialized interface to PVS called TAME (Timed Automata Modeling Environment) which provides automated support for proving properties of I/O automata. A maj...