103 search results - page 5 / 21 » SEU tolerant device, circuit and processor design |
IPPS
2010
IEEE
13 years 4 months ago
2010
IEEE
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasi...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
AIRS
2010
Springer
13 years 4 months ago
2010
Springer
Machine learning algorithms in various forms are now increasingly being used on a variety of portable devices, starting from cell phones to PDAs. They often form a part of standard...
TVLSI
2010
13 years 2 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...