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» SOC Test Scheduling Using Simulated Annealing
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JCP
2006
151views more  JCP 2006»
13 years 7 months ago
Simulated Annealing based Wireless Sensor Network Localization
In this paper, we describe a novel localization algorithm for ad hoc wireless sensor networks. Accurate selforganization and localization capability is a highly desirable character...
Anushiya A. Kannan, Guoqiang Mao, Branka Vucetic
LCN
2005
IEEE
14 years 1 months ago
Simulated Annealing based Localization in Wireless Sensor Network
— In this paper, we describe a novel localization method for ad hoc wireless sensor networks. Accurate selforganization and localization is an essential characteristic of high pe...
Anushiya A. Kannan, Guoqiang Mao, Branka Vucetic
DFT
2005
IEEE
92views VLSI» more  DFT 2005»
14 years 1 months ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
14 years 4 months ago
Test-access mechanism optimization for core-based three-dimensional SOCs
— Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Su...
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yua...
ICCD
2001
IEEE
103views Hardware» more  ICCD 2001»
14 years 4 months ago
Fixed-outline Floorplanning through Better Local Search
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice o...
Saurabh N. Adya, Igor L. Markov