57 search results - page 2 / 12 » SOPA: Selecting the optimal caching policy adaptively |
MICRO
2009
IEEE
14 years 1 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
ICS
2010
Tsinghua U.
13 years 9 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
VLDB
2002
ACM
13 years 6 months ago
2002
ACM
This paper introduces MICP, a novel multiversion integrated cache replacement and prefetching algorithm designed for efficient cache and transaction management in hybrid data deli...
ECRTS
2006
IEEE
14 years 1 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
DATE
2010
IEEE
14 years 5 days ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...