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IPPS
1997
IEEE
14 years 5 days ago
A Reliable Hardware Barrier Synchronization Scheme
Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, ha...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
SIGMETRICS
1996
ACM
118views Hardware» more  SIGMETRICS 1996»
14 years 3 days ago
Integrating Performance Monitoring and Communication in Parallel Computers
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
Margaret Martonosi, David Ofelt, Mark Heinrich
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
14 years 2 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
HPDC
2008
IEEE
14 years 2 months ago
enabling cross-layer optimizations in storage systems with custom metadata
Today, several data-storage systems allow applications to create and manage custom metadata to improve data search and navigability in large-scale storage systems. Our thesis is t...
Elizeu Santos-Neto, Samer Al-Kiswany, Nazareno And...
ISORC
2002
IEEE
14 years 26 days ago
ARTISST: An Extensible and Modular Simulation Tool for Real-Time Systems
ARTISST (ARTISST is a Real-Time System Simulation Tool) is a modular event-driven simulation framework for real-time systems. It is targeted towards the performance evaluation of ...
David Decotigny, Isabelle Puaut