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DATE
2008
IEEE
126views Hardware» more  DATE 2008»
14 years 2 months ago
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs
In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring,...
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimso...
ICC
2007
IEEE
148views Communications» more  ICC 2007»
14 years 1 months ago
On Connectivity and Capacity of Wireless Mesh Networks
—Wireless Mesh Networks represent an interesting technology due to their reliability, broad coverage and relatively easy and inexpensive scalability. The architecture is mainly a...
Ernesto Miorando, Fabrizio Granelli
INFOCOM
2006
IEEE
14 years 1 months ago
The Concurrent Matching Switch Architecture
Abstract— Network operators need high capacity router architectures that can offer scalability, provide throughput guarantees, and maintain packet ordering. However, current cent...
Bill Lin, Isaac Keslassy
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 1 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
ISCAS
2008
IEEE
110views Hardware» more  ISCAS 2008»
14 years 1 months ago
Non-traditional irregular interconnects for massive scale SoC
— By using self-assembling fabrication techniques at the cellular, molecular, or atomic scale, it is nowadays possible to create functional assemblies in a mainly bottom-up way t...
Christof Teuscher, Anders A. Hansson