42 search results - page 5 / 9 » Scalable Hardware Memory Disambiguation for High ILP Process... |
ICCS
2005
Springer
14 years 1 months ago
2005
Springer
Cray X1 Fortran and C/C++ compilers provide a number of loop transformations, notably vectorization and multistreaming, in order to exploit the multistreaming processor (MSP) hard...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
The Cray MTA-2 system provides exceptional performance on a variety of sparse graph algorithms. Unfortunately, it was an extremely expensive platform. Cray is preparing an Eldorad...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high ...
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
ASPLOS
1998
ACM
13 years 11 months ago
1998
ACM
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...