2020 search results - page 19 / 404 » Scalable Instruction-Level Parallelism. |
ISCA
1998
IEEE
14 years 1 months ago
1998
IEEE
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
HICSS
1997
IEEE
14 years 1 months ago
1997
IEEE
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...
ISCAPDCS
2003
13 years 10 months ago
2003
In modern computer systems loops present a great deal of opportunities for increasing Instruction Level and Thread Level Parallelism. Loop unrolling is a technique used to obtain ...
PPOPP
2011
ACM
12 years 11 months ago
2011
ACM
The sparse grid discretization technique enables a compressed representation of higher-dimensional functions. In its original form, it relies heavily on recursion and complex data...
EDBT
2011
ACM
13 years 10 days ago
2011
ACM
The popularity of batch-oriented cluster architectures like Hadoop is on the rise. These batch-based systems successfully achieve high degrees of scalability by carefully allocati...