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ISCA
2002
IEEE
80views Hardware» more  ISCA 2002»
14 years 1 months ago
A Large, Fast Instruction Window for Tolerating Cache Misses
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson K...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 1 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
MICRO
1995
IEEE
125views Hardware» more  MICRO 1995»
14 years 11 days ago
Disjoint eager execution: an optimal form of speculative execution
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
Augustus K. Uht, Vijay Sindagi, Kelley Hall
ESOP
2011
Springer
13 years 10 days ago
Static Analysis of Run-Time Errors in Embedded Critical Parallel C Programs
We present a static analysis by Abstract Interpretation to check for run-time errors in parallel C programs. Following our work on Astr´ee, we focus on embedded critical programs ...
Antoine Miné
TVCG
2012
179views Hardware» more  TVCG 2012»
11 years 11 months ago
Parallel Computation of 2D Morse-Smale Complexes
—The Morse-Smale complex is a useful topological data structure for the analysis and visualization of scalar data. This paper describes an algorithm that processes all mesh eleme...
Nithin Shivashankar, Senthilnathan M, Vijay Natara...