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» Scalable Instruction-Level Parallelism.
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MICRO
1998
IEEE
98views Hardware» more  MICRO 1998»
14 years 1 months ago
Task Selection for a Multiscalar Processor
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
T. N. Vijaykumar, Gurindar S. Sohi
MICRO
1997
IEEE
108views Hardware» more  MICRO 1997»
14 years 1 months ago
Improving the Accuracy and Performance of Memory Communication Through Renaming
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
Gary S. Tyson, Todd M. Austin
PLDI
1996
ACM
14 years 1 months ago
A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints
High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this pape...
Alexandre E. Eichenberger, Edward S. Davidson
CASES
2007
ACM
14 years 26 days ago
Non-transparent debugging for software-pipelined loops
This paper tackles the problem of providing correct information about program variable values in a software-pipelined loop through a non-transparent debugging approach. Since mode...
Hugo Venturini, Frédéric Riss, Jean-...
CPHYSICS
2007
79views more  CPHYSICS 2007»
13 years 8 months ago
Multimillion atom simulations of dynamics of wing cracks and nanoscale damage in glass, and hypervelocity impact damage in ceram
We have developed scalable parallel algorithms for first-principles based predictive atomistic simulations of materials.
Priya Vashishta, Rajiv K. Kalia, Aiichiro Nakano