2020 search results - page 6 / 404 » Scalable Instruction-Level Parallelism. |
ICCD
2002
IEEE
14 years 5 months ago
2002
IEEE
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
MICRO
1992
IEEE
14 years 26 days ago
1992
IEEE
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
APCSAC
2005
IEEE
14 years 2 months ago
2005
IEEE
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...
CONCURRENCY
2006
13 years 8 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
SAMOS
2010
Springer
13 years 6 months ago
2010
Springer
OpenCL is a programming language standard which enables the programmer to express the application by structuring its computation as kernels. The OpenCL compiler is given the explic...