2020 search results - page 9 / 404 » Scalable Instruction-Level Parallelism. |
APCSAC
2003
IEEE
14 years 13 days ago
2003
IEEE
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
VLSID
2004
IEEE
14 years 9 months ago
2004
IEEE
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
CGO
2007
IEEE
14 years 3 months ago
2007
IEEE
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...
EH
2004
IEEE
14 years 16 days ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
PDPTA
2000
13 years 10 months ago
2000
Abstract In this paper, we propose a microprocessor architecture which eciently utilizes nextgeneration semiconductor technology. While the technology makes it possible to integrat...