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» Scalable Memory Hierarchies for Embedded Manycore Systems
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ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
14 years 21 days ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
EMSOFT
2009
Springer
14 years 2 months ago
Flexible filters: load balancing through backpressure for stream programs
Stream processing is a promising paradigm for programming multi-core systems for high-performance embedded applications. We propose flexible filters as a technique that combines...
Rebecca L. Collins, Luca P. Carloni
ISPAN
2005
IEEE
14 years 1 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 7 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
ICASSP
2011
IEEE
12 years 11 months ago
Event classification for personal photo collections
People take more and more photos at different time and different events, however, these photos are often put into one giant folder and they are seldom annotated or organized. As t...
Feng Tang, Daniel Tretter, Chris Willis