656 search results - page 90 / 132 » Scalable Parallel Matrix Multiplication on Distributed Memor... |
IPPS
2003
IEEE
14 years 2 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
IEEEPACT
2009
IEEE
13 years 6 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
CCGRID
2006
IEEE
14 years 2 months ago
2006
IEEE
During the past decade, the scientific community has witnessed the rapid accumulation of gene sequence data and data related to physiology and biochemistry of organisms. Bioinform...
ICPPW
2009
IEEE
14 years 3 months ago
2009
IEEE
A significant fraction of parallel scientific codes are iterative with barriers between iterations or even between phases of the same iteration. The sender of a message is assur...
IEEEPACT
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration is...