Sciweavers

656 search results - page 95 / 132
» Scalable Parallel Matrix Multiplication on Distributed Memor...
Sort
View
HOTI
2002
IEEE
14 years 1 months ago
A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
François Abel, Cyriel Minkenberg, Ronald P....
IPPS
1998
IEEE
14 years 28 days ago
An Evolutionary Approach to Multiprocessor Scheduling of Dependent Tasks
The scheduling of application tasks is a problem that occurs in all multiprocessor systems. This problem becomes even more complicated if the tasks are not independent but are inte...
Roman Nossal
HIPC
2007
Springer
14 years 2 months ago
Self-optimization of Performance-per-Watt for Interleaved Memory Systems
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...
Bithika Khargharia, Salim Hariri, Mazin S. Yousif
SIPS
2008
IEEE
14 years 3 months ago
Efficient mapping of advanced signal processing algorithms on multi-processor architectures
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
Bhavana B. Manjunath, Aaron S. Williams, Chaitali ...
IPPS
2003
IEEE
14 years 1 months ago
Some Modular Adders and Multipliers for Field Programmable Gate Arrays
This paper is devoted to the study of number representations and algorithms leading to efficient implementations of modular adders and multipliers on recent Field Programmable Ar...
Jean-Luc Beuchat