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DATE
2006
IEEE
134views Hardware» more  DATE 2006»
14 years 2 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
ISPEC
2009
Springer
14 years 3 months ago
Hash-Based Key Management Schemes for MPEG4-FGS
We propose two symmetric-key management schemes for the encryption of scalable compressed video content. The schemes are applicable to MPEG-4 Fine Grain Scalability video coding. O...
Mohamed Karroumi, Ayoub Massoudi
ICPP
1990
IEEE
14 years 17 days ago
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
Anoop Gupta, Wolf-Dietrich Weber, Todd C. Mowry
TCSV
2002
148views more  TCSV 2002»
13 years 8 months ago
A full-featured, error-resilient, scalable wavelet video codec based on the set partitioning in hierarchical trees (SPIHT) algor
Compressed video bitstreams require protection from channel errors in a wireless channel. The threedimensional (3-D) SPIHT coder has proved its efficiency and its real-time capabi...
Sungdae Cho, William A. Pearlman
PPOPP
2009
ACM
14 years 9 months ago
A compiler-directed data prefetching scheme for chip multiprocessors
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
Dhruva Chakrabarti, Mahmut T. Kandemir, Mustafa Ka...