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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 22 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
CF
2005
ACM
13 years 9 months ago
Dynamic loop pipelining in data-driven architectures
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
João M. P. Cardoso
FLAIRS
2006
13 years 9 months ago
Designing an AI Elective to Encourage Undergraduate Research
This paper describes the design and execution of a roboticsthemed AI elective at a small liberal arts institution. An important goal of the course is to spark and nurture students...
Zachary Dodds
SBBD
2004
137views Database» more  SBBD 2004»
13 years 9 months ago
A Lock Manager for Collaborative Processing of Natively Stored XML Documents
Today, neither transactional provisions, in general, nor concurrency control, in particular, of DBMS-based processing are tailored to the specific needs of large and collaborative...
Michael Peter Haustein, Theo Härder
ATAL
2010
Springer
13 years 8 months ago
Alternating-time dynamic logic
We propose Alternating-time Dynamic Logic (ADL) as a multi-agent variant of Dynamic Logic in which atomic programs are replaced by coalitions. In ADL, the Dynamic Logic operators ...
Nicolas Troquard, Dirk Walther