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DATE
1998
IEEE
109views Hardware» more  DATE 1998»
14 years 18 hour ago
Cross-Level Hierarchical High-Level Synthesis
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
Oliver Bringmann, Wolfgang Rosenstiel
DATE
2009
IEEE
89views Hardware» more  DATE 2009»
14 years 2 months ago
Exploiting clock skew scheduling for FPGA
- Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain desig...
Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijay...
CN
2010
146views more  CN 2010»
13 years 7 months ago
Badumna: A decentralised network engine for virtual environments
Many of today's virtual environment applications, such as massively multi-player online games, involve a large and rapidly changing set of users. The server-based architectur...
Santosh Kulkarni, Scott Douglas, David Churchill
HT
2009
ACM
14 years 2 months ago
The scalable hyperlink store
This paper describes the Scalable Hyperlink Store, a distributed in-memory “database” for storing large portions of the web graph. SHS is an enabler for research on structural...
Marc Najork
IPPS
1999
IEEE
14 years 1 days ago
Average-Case Analysis of Isospeed Scalability of Parallel Computations on Multiprocessors
We investigate the average-case speed and scalability of parallel algorithms executing on multiprocessors. Our performance metrics are average-speed and isospeed scalability. By m...
Keqin Li, Xian-He Sun