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DELTA
2008
IEEE
14 years 23 days ago
Dynamic Co-operative Intelligent Memory
As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. In order to bridge this gap, many met...
Xiaoyong Wen, Faycal Bensaali, Reza Sotudeh
IEEEPACT
2007
IEEE
14 years 5 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
CASES
2007
ACM
14 years 3 months ago
Rethinking custom ISE identification: a new processor-agnostic method
The last decade has witnessed the emergence of the Application Specific Instruction-set Processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user...
Ajay K. Verma, Philip Brisk, Paolo Ienne
IJPP
2006
82views more  IJPP 2006»
13 years 11 months ago
Supporting Microthread Scheduling and Synchronisation in CMPs
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...
Ian Bell, Nabil Hasasneh, Chris R. Jesshope
JMLR
2010
170views more  JMLR 2010»
13 years 9 months ago
A Streaming Parallel Decision Tree Algorithm
A new algorithm for building decision tree classifiers is proposed. The algorithm is executed in a distributed environment and is especially designed for classifying large datase...
Yael Ben-Haim, Elad Tom-Tov