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MICRO
2003
IEEE
132views Hardware» more  MICRO 2003»
14 years 20 days ago
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasa...
MICRO
2003
IEEE
96views Hardware» more  MICRO 2003»
14 years 20 days ago
Scalable Hardware Memory Disambiguation for High ILP Processors
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
Simha Sethumadhavan, Rajagopalan Desikan, Doug Bur...
ICALP
2010
Springer
13 years 11 months ago
Scalably Scheduling Power-Heterogeneous Processors
We show that a natural online algorithm for scheduling jobs on a heterogeneous multiprocessor, with arbitrary power functions, is scalable for the objective function of weighted ï¬...
Anupam Gupta, Ravishankar Krishnaswamy, Kirk Pruhs
ICMCS
2006
IEEE
141views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Scalability of Multimedia Applications on Next-Generation Processors
In the near future, the majority of personal computers are expected to have several processing units. This is referred to as Core Multiprocessing (CMP). Furthermore, each of the c...
Guy Amit, Yaron Caspi, Ran Vitale, Adi Pinhas
CASES
2004
ACM
13 years 11 months ago
Scalable custom instructions identification for instruction-set extensible processors
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. However, it is computationally expensive to automaticall...
Pan Yu, Tulika Mitra