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PATMOS
2005
Springer
14 years 3 months ago
A Power-Efficient and Scalable Load-Store Queue Design
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...
Fernando Castro, Daniel Chaver, Luis Piñuel...
SIAMCOMP
1998
117views more  SIAMCOMP 1998»
13 years 9 months ago
The Queue-Read Queue-Write PRAM Model: Accounting for Contention in Parallel Algorithms
This paper introduces the queue-read, queue-write (qrqw) parallel random access machine (pram) model, which permits concurrent reading and writing to shared memory locations, but ...
Phillip B. Gibbons, Yossi Matias, Vijaya Ramachand...
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Mixed-clock issue queue design for energy aware, high-performance cores
- Globally-Asynchronous, Locally-Synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal ...
Venkata Syam P. Rapaka, Emil Talpes, Diana Marcule...
INFOCOM
2000
IEEE
14 years 2 months ago
Fast and Scalable Priority Queue Architecture for High-Speed Network Switches
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...
Ranjita Bhagwan, Bill Lin
ICC
2008
IEEE
132views Communications» more  ICC 2008»
14 years 4 months ago
An On-Off Queue Control Mechanism for Scalable Video Streaming over the IEEE 802.11e WLAN
— In this paper, we study the issue of scalable video streaming over IEEE 802.11e EDCA WLANs. Our basic idea is to control the number of “active” nodes on the channel in orde...
Yu Zhang, Chuan Heng Foh, Jianfei Cai