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HPCA
2012
IEEE
12 years 5 months ago
Power balanced pipelines
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
John Sartori, Ben Ahrens, Rakesh Kumar
HPCA
2008
IEEE
14 years 10 months ago
Single-level integrity and confidentiality protection for distributed shared memory multiprocessors
Multiprocessor computer systems are currently widely used in commercial settings to run critical applications. These applications often operate on sensitive data such as customer ...
Brian Rogers, Chenyu Yan, Siddhartha Chhabra, Milo...
EUROPAR
2010
Springer
13 years 10 months ago
Multi-GPU and Multi-CPU Parallelization for Interactive Physics Simulations
Today, it is possible to associate multiple CPUs and multiple GPUs in a single shared memory architecture. Using these resources efficiently in a seamless way is a challenging issu...
Everton Hermann, Bruno Raffin, François Fau...
SIGMOD
2012
ACM
276views Database» more  SIGMOD 2012»
12 years 8 days ago
SCARAB: scaling reachability computation on large graphs
Most of the existing reachability indices perform well on small- to medium- size graphs, but reach a scalability bottleneck around one million vertices/edges. As graphs become inc...
Ruoming Jin, Ning Ruan, Saikat Dey, Jeffrey Xu Yu
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
14 years 4 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...