433 search results - page 13 / 87 » Scale in Chip Interconnect requires Network Technology |
TCAD
2010
13 years 2 months ago
2010
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient netwo...
HIPC
2005
Springer
14 years 28 days ago
2005
Springer
We explore the opportunities offered by current and forthcoming VLSI technologies to on-chip multiprocessing for Quantum Chromo Dynamics (QCD), a computational grand challenge for ...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
DSD
2002
IEEE
14 years 11 days ago
2002
IEEE
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...