433 search results - page 14 / 87 » Scale in Chip Interconnect requires Network Technology |
TVLSI
2008
13 years 8 months ago
2008
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
ICCAD
1997
IEEE
14 years 22 days ago
1997
IEEE
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
DAC
1999
ACM
14 years 25 days ago
1999
ACM
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
IWANN
2007
Springer
14 years 2 months ago
2007
Springer
This paper presents a network architecture to interconnect mixed-signal VLSI1 integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. ...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
- The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be develo...