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» Scale in Chip Interconnect requires Network Technology
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ADHOC
2008
135views more  ADHOC 2008»
13 years 11 months ago
Rapid design and evaluation framework for wireless sensor networks
The diversity of applications and typically scarce node resources set very tight constraints to Wireless Sensor Networks (WSN). It is not possible to fulfill all requirements with...
Mauri Kuorilehto, Marko Hännikäinen, Tim...
DAC
2005
ACM
14 years 11 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
WWW
2009
ACM
14 years 11 months ago
Anycast-aware transport for content delivery networks
Anycast-based content delivery networks (CDNs) have many properties that make them ideal for the large scale distribution of content on the Internet. However, because routing chan...
Zakaria Al-Qudah, Seungjoon Lee, Michael Rabinovic...
MMNS
2003
143views Multimedia» more  MMNS 2003»
14 years 6 days ago
M3G: A Mobile Multicast Multimedia Gateway for Seamless IPv4/IPv6 Transition
A growing interest in third generation wireless IP network and service technologies, push up the demand on IPv6 transition. Most of these services require mobility, multicast and m...
Yassine Hadjadj Aoul, Daniel Negru, Abdelhamid Naf...
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
14 years 5 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...