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» Scale in Chip Interconnect requires Network Technology
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NOCS
2010
IEEE
13 years 5 months ago
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global cloc...
Michael N. Horak, Steven M. Nowick, Matthew Carlbe...
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
14 years 1 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
TC
2008
13 years 7 months ago
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
Assaf Shacham, Keren Bergman, Luca P. Carloni
COMPUTER
2002
129views more  COMPUTER 2002»
13 years 7 months ago
Networks on Chips: A New SoC Paradigm
of abstraction and coarse granularity and distributed communication control. Focusing on using probabilistic metrics such as average values or variance to quantify design objective...
Luca Benini, Giovanni De Micheli
ISQED
2007
IEEE
206views Hardware» more  ISQED 2007»
14 years 1 months ago
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, ...