2800 search results - page 142 / 560 » Scaling RDF with time |
134
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ICCAD
2005
IEEE
16 years 1 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
140
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ASPDAC
2006
ACM
15 years 10 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
120
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CCGRID
2004
IEEE
15 years 8 months ago
2004
IEEE
In a Computational Grid which consists of many computer clusters, job start time predictions are useful to guide resource selections and balance the workload distribution. However...
272
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ICDE
2005
IEEE
16 years 6 months ago
2005
IEEE
Efficiently and accurately searching for similarities among time series and discovering interesting patterns is an important and non-trivial problem. In this paper, we introduce a...
129
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ICCAD
2003
IEEE
16 years 1 months ago
2003
IEEE
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...