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» Scaling Soft Processor Systems
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RTS
2010
79views more  RTS 2010»
13 years 6 months ago
Spin-based reader-writer synchronization for multiprocessor real-time systems
Reader preference, writer preference, and task-fair reader-writer locks are shown to cause undue blocking in multiprocessor real-time systems. Phase-fair reader writer locks, a ne...
Björn B. Brandenburg, James H. Anderson
DATE
2005
IEEE
91views Hardware» more  DATE 2005»
14 years 1 months ago
Reliability-Centric High-Level Synthesis
Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density c...
Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, ...
VLSISP
2010
102views more  VLSISP 2010»
13 years 6 months ago
A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal Processing Systems
Fine-grained accelerators have the potential to deliver significant benefits in various platforms for embedded signal processing. Due to the moderate complexity of their targeted o...
Jani Boutellier, Shuvra S. Bhattacharyya, Olli Sil...
FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
12 years 11 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...
DAC
2010
ACM
13 years 11 months ago
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme
System optimization techniques based on dynamic voltage scaling (DVS) are widely used with the aim of reducing processor energy consumption. Inter-task DVS assigns the same voltag...
Weixun Wang, Prabhat Mishra