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ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 16 days ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
DAC
2005
ACM
14 years 8 months ago
System-level energy-efficient dynamic task scheduling
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
Jianli Zhuo, Chaitali Chakrabarti
ISLPED
2006
ACM
145views Hardware» more  ISLPED 2006»
14 years 1 months ago
An optimal analytical solution for processor speed control with thermal constraints
As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (D...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
IEEEPACT
2005
IEEE
14 years 1 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
ISLPED
2007
ACM
110views Hardware» more  ISLPED 2007»
13 years 9 months ago
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
Fine-grained dynamic voltage/frequency scaling (DVFS) demonstrates great promise for improving the energy-efficiency of chip-multiprocessors (CMPs), which have emerged as a popula...
Sebastian Herbert, Diana Marculescu