Sciweavers

521 search results - page 43 / 105
» Scaling Soft Processor Systems
Sort
View
PDPTA
1996
13 years 9 months ago
Exploiting Task-Level Parallelism Using pTask
This paper presents pTask-- a system that allows users to automatically exploit dynamic task-level parallelism in sequential array-based C programs. The system employs compiler an...
Tarek S. Abdelrahman, Sum Huynh
ICS
2010
Tsinghua U.
13 years 10 months ago
Clustering performance data efficiently at massive scales
Existing supercomputers have hundreds of thousands of processor cores, and future systems may have hundreds of millions. Developers need detailed performance measurements to tune ...
Todd Gamblin, Bronis R. de Supinski, Martin Schulz...
IPPS
2006
IEEE
14 years 1 months ago
A multiprocessor architecture for the massively parallel model GCA
The GCA (Global Cellular Automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical...
Wolfgang Heenes, Rolf Hoffmann, Johannes Jendrsczo...
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
13 years 11 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
DAC
1998
ACM
13 years 12 months ago
A Tool for Performance Estimation of Networked Embedded End-systems
Networked embedded systems are expected to support adaptive streaming audio/video applications with soft real-time constraints. These systems can be designed in a cost efficient ...
Asawaree Kalavade, Pratyush Moghé