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ARC
2009
Springer
165views Hardware» more  ARC 2009»
14 years 2 months ago
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
Xu Guo, Patrick Schaumont
DAC
2008
ACM
13 years 9 months ago
Protecting bus-based hardware IP by secret sharing
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
VLSISP
2008
132views more  VLSISP 2008»
13 years 7 months ago
Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications
Modern multimedia applications usually have real-time constraints and they are implemented using application-domain specific embedded processors. Dimensioning a system requires acc...
Stefan Valentin Gheorghita, Twan Basten, Henk Corp...
SUTC
2008
IEEE
14 years 2 months ago
Power-Aware Real-Time Scheduling upon Identical Multiprocessor Platforms
In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard real-time tasks using dynamic voltage scaling upon multiprocessor platforms. We propose ...
Vincent Nélis, Joël Goossens, Raymond ...
SAINT
2006
IEEE
14 years 1 months ago
Energy-Efficient Scheme for Multiprocessor-Based Router Linecards
– In support of continuously increasing line rates and various Internet services, multiprocessor-based linecards have appeared in next-generation routers, significantly improving...
Malcolm Mandviwalla, Nian-Feng Tzeng