Sciweavers

860 search results - page 92 / 172
» Scaling Up Software Architecture Evaluation Processes
Sort
View
HPCA
2007
IEEE
14 years 8 months ago
Implications of Device Timing Variability on Full Chip Timing
As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This pap...
Murali Annavaram, Ed Grochowski, Paul Reed
GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
14 years 1 months ago
A high speed and leakage-tolerant domino logic for high fan-in gates
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peirav...
IR
2010
13 years 5 months ago
Efficient algorithms for ranking with SVMs
RankSVM (Herbrich et al, 2000; Joachims, 2002) is a pairwise method for designing ranking models. SVMLight is the only publicly available software for RankSVM. It is slow and, due ...
Olivier Chapelle, S. Sathiya Keerthi
IAJIT
2007
90views more  IAJIT 2007»
13 years 7 months ago
Software Reuse for Mobile Robot Applications Through Analysis Patterns
: Software analysis pattern is an approach of software reuse which provides a way to reuse expertise that can be used across domains at early level of development. Developing softw...
Dayang N. A. Jawawi, Safaai Deris, Rosbi Mamat
CF
2007
ACM
13 years 12 months ago
Fast compiler optimisation evaluation using code-feature based performance prediction
Performance tuning is an important and time consuming task which may have to be repeated for each new application and platform. Although iterative optimisation can automate this p...
Christophe Dubach, John Cavazos, Björn Franke...